Phase slips are an increasing problem with high speed serial data links. The higher the bitrates, the more prone the links are to suffer from phase slip problems. Slips may be caused by the clock and data recovery units (CDRs) having to work with lower and lower signal-to-amplitude and signal-to-phase noise margins.
Currently, reliably detecting and analyzing phase slips occurring on high speed data links is difficult because even though a data error resulting from phase slips are detectable, there may be several possible causes of the data errors. As such, testing and diagnosis tools may mischaracterize the true cause of the data error. For example, slips are oftentimes mischaracterized as error bursts. This can be misleading since the root causes for error bursts are very different from the root causes for phase slips in many cases. The problem is often exacerbated by the errors occurring infrequently (such as only once a day) and because slips may be dependent on the specific data pattern being processed. Therefore, diagnosing and fixing slip induced errors is often difficult and time consuming.